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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク High-speed transceiver logic ： ウィキペディア英語版 High-speed transceiver logic High-speed transceiver logic or HSTL is a technology-independent standard for signaling between integrated circuits.〔(【引用サイトリンク】 date=1995-08-01 )〕 The nominal signaling range is 0 V to 1.5 V, though variations are allowed, and signals may be single-ended or differential. It is designed for operation beyond 180 MHz. The following classes are defined by standard EIA/JESD8-6 from EIA/JEDEC: *Class I (unterminated, or symmetrically parallel terminated) *Class II (series terminated) *Class III (asymmetrically parallel terminated) *Class IV (asymmetrically double parallel terminated) Note: ''Symmetric parallel termination'' means that the termination resistor at the load is connected to half the output buffer's supply voltage. ''Double parallel termination'' means that parallel termination resistors are fitted at both ends of the transmission line. ==See also== *Stub Series Terminated Logic - SSTL 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「High-speed transceiver logic」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.